1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and in particular, to a method of manufacturing a semiconductor device applied to a power device.
2. Description of the Background Art
In semiconductor devices, implementing a higher-density package by three-dimensional mounting or the like has been developed. Accordingly, reduction of a thickness of a wafer has been required, and the thickness of a wafer at the time of completion of a process for a semiconductor device has been reduced to a thickness of about 25 μm.
Semiconductor devices include power devices such as an IGBT (Insulated Gate Bipolar Transistor) and an MOSFET (Metal Oxide Semiconductor Field Effective Transistor). These power devices (power semiconductor devices) are widely used, for example, as an inverter circuit for an industrial motor, an automotive motor, or the like, a power supply device for a large-capacity server, or a semiconductor switch for an uninterruptible power supply device or the like.
In such a power semiconductor device, a semiconductor substrate is worked to be thin to improve energization characteristics represented by ON characteristics and the like. In recent years, an ultra-thin semiconductor substrate based on an FZ (Floating Zone) wafer has been used to improve cost and characteristic aspects. For example, in an IGBT with a withstand voltage of 600 V, it is necessary to reduce the thickness of a semiconductor substrate to about 60 to 70 μm.
Generally, a semiconductor substrate is worked to be thin by back grinding, polishing with a polish, or mechanical polishing. When a semiconductor substrate is worked to be thin by such a technique, distortion occurs in the semiconductor substrate. Therefore, to remove a portion where distortion occurs, wet etching treatment or dry etching treatment is performed on a rear surface of the semiconductor substrate.
Further, since it is necessary to form an implantation layer and rear surface electrodes on a rear surface of a semiconductor substrate in the power semiconductor device, ion implantation treatment, sputtering treatment, and heat treatment are performed on the rear surface of the semiconductor substrate. However, since such treatment is performed after working the semiconductor substrate to be thin, there is a problem that the semiconductor substrate is likely to crack during the treatment.
To suppress cracking of a semiconductor substrate as described above, for example, Japanese Patent Laying-Open No. 2007-335659 proposes a technique of increasing the strength of a semiconductor substrate by providing a level difference (thickness) on a rear surface of an outer peripheral end portion of the semiconductor substrate.
With this technique, however, when wet etching treatment is performed on the rear surface of the semiconductor substrate to remove work distortion due to grinding or the like, a chemical solution may be scattered by the level difference at the outer peripheral end portion. Further, when the semiconductor substrate is attached to a dicing frame in the step of dicing a wafer into individual chips, air bubbles may enter between the semiconductor substrate and a tape. Furthermore, there is also a possibility that rear surface electrodes made of aluminum formed on the rear surface of the semiconductor substrate may be eroded when the level difference is removed, or that the yield of chips obtained may be decreased by providing the level difference.
In addition, reasons for causing the semiconductor substrate to crack easily include, in particular, that the outer peripheral end portion of the semiconductor substrate becomes like the edge of a knife. Since the outer peripheral end portion of the semiconductor substrate is generally chamfered to have a cross section in the shape of a portion of an ellipse, the outer peripheral portion of the semiconductor substrate becomes like the edge of a knife when the semiconductor substrate is worked to be thin by polishing or the like, and thus the edge portion is likely to chip or crack.
To suppress chipping or the like of an outer peripheral end portion of a semiconductor substrate as described above, Japanese Patent Laying-Open No. 2003-059878 proposes a technique of polishing an outer peripheral end portion of a semiconductor substrate. In this case, however, the outer peripheral end portion of the semiconductor substrate may be etched like the edge of a knife again by wet etching for removing work distortion, as described below.
Specifically, to remove work distortion caused in the semiconductor substrate by a back grinding step when the thickness of the semiconductor substrate is reduced, a stress relief step is required. In the stress relief step, wet etching treatment with a chemical solution using nitric-hydrofluoric acid is performed on a rear surface of the semiconductor substrate.
On this occasion, nitric-hydrofluoric acid may reach a front surface side of the outer peripheral end portion from the rear surface of the semiconductor substrate. Thus, the front surface side of the outer peripheral end portion of the semiconductor substrate is etched with the reaching nitric-hydrofluoric acid, and the outer peripheral end portion of the semiconductor substrate becomes like the edge of a knife again. This has caused a problem that the outer peripheral end portion of the semiconductor substrate is likely to chip or crack.